CP464: Selected Topics in Computer Hardware

About this course ...
Faculty of Science General Regulations

Sample Processor Reference Manuals

• Motorola M68000 Family Programmer’s Reference Manual
  [pdf, 646 pages; Motorola ]
  
  
• COP8SBR9/SCR9/SDR9 Flash based microcontrollers
  [pdf, 80 pages; National Semiconductor]
  
  
• PICmicro® 18C MCU Family Reference Manual
  [pdf, 976pp; ©2000 Microchip Technology Inc.]
  
  
• Pentium® Processor Family Developer’s Manual
  [pdf, 1032 pages; Intel]
  
  
• IA-32 Intel® Architecture Software Developer’s Manual
  [pdf, 966 pages; Intel]
  
  
• Intel® Itanium® Architecture Software Developer's Manual
  [pdf, 250pp; Intel]

VHDL Reference Material

• If you need a VHDL refresher see:
  VHDL Review 1, 2, 3 [pdf].
• VHDL Language Guide [© 2005, Altium Limited.]
• CP319 Digital System Design

Development Environment

• Altera® Quartus ® II Software and Documentation
• Altera Development Boards
• Quartus II Setting File with Pin Assignments: DE2.qsf
  [from Altera to define pins for the DE2 board]

• Assembly Language Design:
  • Instruction Set and Syntax [ pdf , html ]
  • Addressing Modes [ pdf , html ]
• Machine Code Design

• Very Small Processor - Phase 0 [due Tuesday January 10]
  • Phase 0 Marking Scheme
• Memory - Part 1 [complete by end of next week; do before Memory - Part 2] -- modified January 5 11:30am

Addressing Modes: see Section 2.2 Effective Addressing Modes from Motorola M68000 Family Programmer’s Reference Manual for an example of a well written addressing mode description.

Condition codes: examples of program control and condition codes/flags

• install Quartus II Web Edition (v11.0, SP1) software on home system
• Work through How to run a testbench using Altera-ModelSim
• Quartus II Setting File with Pin Assignments DE2.qsf [from Altera to define pins for the DE2 board]
  
  
• Memory 101 [from CP/PC319]
• Cyclone II Memory Guide - includes timing diagrams

• Machine Code Approaches
  • examples:
    • IBM370
    • M68000
    • MIPS
    • RISC-I
    • SPARC
• Case Studies
  • examples:
    • Intel x86
    • M68000
    • PDP-11
• Dataflow Design 1

• Very Small Processor - Phase 1 [due by January 20th or 23rd]
  • Phase 1 Marking Scheme
    
• Memory - Part 2 [demonstrate parts 1 & 2 by January 20th]

Design Philosophy Behind Motorola's MC68000

• Part 1: A 16-bit processor with multiple 32-bit registers. [Thomas W. Starnes, Motorola, April 1983 © BYTE Publications Inc]
• Part 2: Data-movement, arithmetic, and logic instructions [Thomas W. Starnes, Motorola, May 1983 © BYTE Publications Inc]
• Part 3: Advanced instructions [Thomas W. Starnes, Motorola, June 1983 © BYTE Publications Inc]

• VAX-11 Architecture Reference Manual [pdf]
• Series 32000 Programmer's Reference Manual [pdf]
• M68000 Programmer's Reference Manual [pdf]

• Dataflow Design 2
• Case Studies
• Instruction Execution

• Very Small Processor - Phase 2 [due week of February 1st]
  • Phase 2 Marking Scheme

• Instruction Execution 2
• Instructruction Set Program (example)

• Very Small Processor - Phase 3 [due week of February 7th]
  • Phase 3 Marking Scheme

• correct implementation in VHDL

• System on a Chip (SoC)

• Basic Computer System for the Altera DE2 Board
• Lab 1 and Lab 2 with design files: lab1_part2.s , nios_macros.s , part2.ncf
• Lab3 with design files: lab3_part1.s , nios_macros.s , part1.ncf

• Introduction to the Altera Nios II Soft Processor [Altera, May 2011]
• Nios II Processor Reference Handbook [Altera, May 2011]
• Altera Monitor Program Tutorial [Altera, May 2011]

• Using SOPC Builder to Implement a Computer System [disregard references to lab 4]
  • group project
  • demonstration is part IV

• Computational Models
• Parallel Processing

• Instruction Level Processing

• Pipelined Processors
• Superscalar Processors

• Decisive Aspects in the Evolution of Microprocessors [pdf, 41pp; D. Sima]
• Deterministic Features in the Evolution of Microprocessors [pdf, 30pp; D. Sima]

• The Design Space of Register Renaming Techniques in Superscalar Processors [pdf, 46pp; D. Sima]
• The Design Space of Shelving [pdf, 46pp; D. Sima]
• Generic Datapath Alternatives of Advanced Superscalar [pdf, 24pp; D. Sima]

• Superscalar CPU Simulator v1.1 [zip; © Árpád Miklós, Budapest, Hungary, 2001]
• VSIM Superscalar CPU Simulator v2.0 [zip with simulator and Delphi real time library] [© Árpád Miklós, Budapest, Hungary,2001]
• VSIM - A Superscalar CPU Simulator [pdf; 12pp, © Árpád Miklós, Dezsö Sima, Budapest, Hungary, 2002]

• Sample exam questions: Winter 2004 [pdf] and screen shot [jpg]
• final exam is 1-1.5 hours long
• exam is closed book
• to be scheduled by class